Digital ASIC
Completed May 20261000BASE-T Gigabit Ethernet Digital TX Front End
RTL-to-GDSII implementation of the IEEE 802.3 Clause 40 transmit datapath in SkyWater 130nm.
Tofic Esses
Chip & systems design engineer
UC Berkeley MEng EECS graduate. I work across the stack, from RTL and microarchitecture to physical implementation, analog circuits, and full embedded hardware systems.
Open to Digital/ASIC and System-Level Design roles.
Based in the Bay Area, United States.
Education
- Master of Engineering, Electrical Engineering & Computer Sciences UC Berkeley Concentration in physical electronics and integrated circuits
- Bachelor of Engineering, Electrical Engineering McGill University
Chip Design
Microarchitecture
Completed December 2025RISC-V RV32I Processor
Three-stage pipelined RV32I core with operand forwarding and direct-mapped caches, synthesized and placed-and-routed in SkyWater 130nm.
Analog IC
Completed December 2025Display Driver Op-Amp
Two-stage amplifier with telescopic cascode input and Class AB output for a 10-bit DAC display driver, designed and simulated in GPDK045.
Analog Circuit Design
September–December 2024Discrete BJT Operational Amplifier
General-purpose three-stage op-amp built from bipolar transistors, hand-calculated, simulated in LTspice, and validated stage-by-stage on a breadboard.
System Level Design
Mixed-Signal System
Completed May 2026Compressed Ultrasound Imaging System
Eight-PMUT compressed-sensing 3D ultrasound imager on a single 6-layer mixed-signal PCB, HV pulser transmit path, low-noise receive front end, and simultaneous-sampling data acquisition.
Medical Device · Firmware + Hardware
January–December 2024Modular Scintillation Detector
Cost-efficient, modular, multi-channel scintillation detector for automated PET radiopharmaceutical synthesis, firmware, hardware, and 3D-printed enclosure.
Embedded Systems
January–March 2024Embedded Systems Applications
Six Arduino sensor-kit applications, each driven by a hand-designed state machine, built for McGill's Embedded Systems (ECSE 421) labs.
Embedded Systems
April 2023Digital Ball-in-Maze Puzzle
A ball-in-maze game on an STM32, IMU-driven ball physics smoothed with a Kalman filter and rendered on an OLED. Open-ended ECSE 444 final project.
Other
Software
August 2022Othello (Reversi)
Java implementation of Othello with a minimax computer opponent and full game-state review backed by a doubly linked list.
Work
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Feb 2026 – May 2026
Graduate Student Researcher · PCB Designer
Rayne Research Group · UC Berkeley
- Designed a flex-rigid, miniaturized PCB for a tactile-sensing system integrated into a robotic hand, ensuring signal integrity.
- Integrated PZT sensors with a signal-processing pipeline — TIA, multiplexers, buffers, and an ADC — alongside mechanical and materials engineers.
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Sep 2025 – May 2026
M.Eng Capstone · Hardware Designer
Berkeley Sensor & Actuator Center · UC Berkeley
- Designed a 6-layer mixed-signal PCB for piezo (PMUT) signal acquisition on a full-stack ultrasound spatial-imaging device, designing for assembly, test, and programmability.
- Performed board bring-up — power delivery, ICs, and firmware — to achieve full electronic-system functionality.
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May 2024 – Aug 2024
Applications Development Intern
Silicon Labs · Montreal, Canada
- Built end-device applications in C/C++ and Bash across SoC architectures, enabling OTA and bootloader updates over the IEEE 802.15.4 Thread protocol.
- Implemented the first Matter Scenes Cluster (CSA-IoT) application, and wrote a Bash automation script for SDK version switching that boosted team productivity.
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Sep 2023 – Apr 2024
Teaching Assistant · Electronics
McGill University · Montreal, Canada
- Led weekly discussions, labs, and office hours supporting 100+ students in electronics.
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May 2022 – Aug 2022
RTL Design & Validation Intern
Matrox Imaging (now Zebra Technologies) · Montreal, Canada
- Implemented image-processing pipelines on Xilinx FPGAs in VHDL for new framegrabber designs in industrial inspection, adhering to the Camera Link protocol.
- Engineered C++ automated test suites to probe image-acquisition edge cases, verified through waveform analysis.
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Jan 2022 – Apr 2022
Undergraduate Researcher
Heterogeneous Integration Knowledge Team · Montreal, Canada
- Researched floor-planning algorithms to optimize thermal management in 3D integrated circuits.
- Studied numerical methods such as simulated annealing to find local and global minima of a cost function.
- Implemented simulated annealing in C++ to demonstrate optimized parameter fine-tuning.
Working across RTL and chip design, analog and mixed-signal hardware, embedded firmware, and PCB engineering — in both industry and research — lets me reason about a design holistically, from transistor to full system, and see where to innovate and optimize across the stack.